FOUNDERS OF INTEL
The Men Behind the Microchip: The Early Years of Intel Founders Robert Noyce and Gordon Moore
As self-described �accidental entrepreneurs,� Robert Noyce and Gordon Moore created what would become by far the foremost semiconductor maker in the world. They didn�t set out to create a billion dollar company or to transform an industry, but that is exactly what the pair did when they founded Intel in 1968. Though best known for its Pentium and Celeron microprocessors that can be found in more than three-quarters of the new PCs that come today, Intel also makes flash memories and embedded semiconductors. Now, with over $35 billion in revenue and annual growth standing at 13.5 percent, the legacy left by Noyce and Moore remains one of the strongest examples of innovation and entrepreneurship in the 21st century.
Gordon Earle Moore was born on January 3, 1929, in San Francisco, California. From an early age, he discovered his natural curiosity and passion for science. In fact, his hearing would later be damaged as a result of his passion for creating loud explosions with the materials he found in chemistry sets as a young boy. �A couple of ounces of dynamite makes for a great firecracker,� he jokes.
That passion stayed with Moore as he continued on through junior high school and on to university. �From the time I was in junior high school I decided I wanted to be a chemist,� says Moore. �I didn�t quite know what a chemist was, but I kept it up and got my PhD in physical chemistry.� In 1950, Moore graduated with his PhD from the California Institute of Technology.
Robert Noyce, now nicknamed �the Mayor of Silicon Valley,� was born in Burlington, Iowa, on December 12, 1927. The son of a preacher, Noyce majored in physics at Grinnell College. Always the charismatic leader of the crowd, Noyce almost got himself expelled for a prank he pulled. After stealing a pig from a nearby college for a school luau and slaughtering it in one of the college halls, Noyce was saved from expulsion only thanks to the efforts of his physics professor, Grant Gale.
While a student at Grinnell, Gale had gotten a hold of two of the very first transistors manufactured by Bell Labs and he introduced them to Noyce who was immediately hooked. Noyce went to the Massachusetts Institute of Technology to obtain his PhD in physics, only to find he knew more about transistors than did many of his professors. In 1953, Noyce received his PhD and, after a brief stint making transistors for the electronics firm Philco, decided he wanted to work at Shockley Semiconductor Laboratory. In a single day, Noyce packed up his wife and two children, flew out to California, and bought a house � all before he had even gone to visit Shockley to ask for a job.
Shockley wound up hiring Noyce, and it was while working here that he would meet his future Intel co-founder, Moore. In little time, visions and egos were clashing at Shockley. Seven of the company�s young researchers, including Moore, who had been hired out of Caltech, decided they were going to leave and start up a company on their own. Together, in 1957, the �Traitorous Eight� left Shockley and founded Fairchild Semiconductor. It would be the beginnings of a success that neither Moore nor Noyce could have ever predicted.
Moore's Law
Formulations of Moore's Law
The most popular formulation is of the doubling of the number of transistors on integrated circuits every 18 months. At the end of the 1970s, Moore's Law became known as the limit for the number of transistors on the most complex chips. However, it is also common to cite Moore's Law to refer to the rapidly continuing advance in computing power per unit cost, because increase in transistor count is also a rough measure of computer processing power. On this basis, the power of computers per unit cost - or more colloquially, "bangs per buck" - doubles every 24 months (or, equivalently, increases 32-fold in 10 years).
A similar law (sometimes called Kryder's Law) has held for hard disk storage cost per unit of information. The rate of progression in disk storage over the past decades has actually sped up more than once, corresponding to the utilization of error correcting codes, the magnetoresistive effect and the giant magnetoresistive effect. The current rate of increase in hard drive capacity is roughly similar to the rate of increase in transistor count. However, recent trends show that this rate is dropping, and has not been met for the last three years. See Hard disk capacity.
Another version states that RAM storage capacity increases at the same rate as processing power.
Similarly, Barry Hendy of Kodak Australia has plotted the "pixels per dollar" as a basic measure of value for a digital camera, demonstrating the historical linearity (on a log scale) of this market and the opportunity to predict the future trend of digital camera price and resolution.
Due to the mathematical power of exponential growth (similar to the financial power of compound interest), seemingly minor fluctuations in the relative growth rates of CPU performance, RAM capacity, and disk space per dollar have caused the relative costs of these three fundamental computing resources to shift markedly over the years, which in turn has caused significant changes in programming styles. For many programming problems, the developer has to decide on numerous time-space tradeoffs, and throughout the history of computing these choices have been strongly influenced by the shifting relative costs of CPU cycles versus storage space.
An industry driver
Although Moore's Law was initially made in the form of an observation and forecast, the more widely it became accepted, the more it served as a goal for an entire industry. This drove both marketing and engineering departments of semiconductor manufacturers to focus enormous energy aiming for the specified increase in processing power that it was presumed one or more of their competitors would soon actually attain. In this regard, it can be viewed as a self-fulfilling prophecy.
The implications of Moore's Law for computer component suppliers are very significant. A typical major design project (such as an all-new CPU or hard drive) takes between two and five years to reach production-ready status. In consequence, component manufacturers face enormous timescale pressures—just a few weeks of delay in a major project can spell the difference between great success and massive losses, even bankruptcy. Expressed as "a doubling every 18 months", Moore's Law suggests the phenomenal progress of technology in recent years. Expressed on a shorter timescale, however, Moore's Law equates to an average performance improvement in the industry as a whole of close to 1% per week. For a manufacturer competing in the competitive CPU market, a new product that is expected to take three years to develop and is just three or four months late is 10 to 15% slower, bulkier, or lower in storage capacity than the directly competing products, and is usually unsellable. (If instead we accept that performance doubles every 24 months, rather than every 18 months, a 3 to 4 month delay would mean 8 to 11% less performance.)
Future trends
As of Q1 2007, most PC processors are currently fabricated on a 65nm process, with some 90 nm chips still left in retail channels, mostly from AMD, as they are slightly behind Intel in transitioning away from 90 nm. On January 27, 2007, Intel demonstrated a working 45nm chip which they intend to begin mass-producing in late 2007. This new family of chips has been given the codename "Penryn". A decade ago, chips were built using a 500 nm process. (The diameter of an atom is in the order of 0.1 nm.) Companies are working on using nanotechnology to solve the complex engineering problems involved in producing chips at the 30 nm and smaller levels—a process that may postpone the industry meeting the limits of Moore's Law.
Recent computer industry technology "roadmaps" predict (as of 2001) that Moore's Law will continue for several chip generations. Depending on the doubling time used in the calculations, this could mean up to 100 fold increase in transistor counts on a chip in a decade. The semiconductor industry technology roadmap uses a three-year doubling time for microprocessors, leading to about tenfold increase in a decade.
In early 2006, IBM researchers announced that they had developed a technique to print circuitry only 29.9 nm wide using deep-ultraviolet (DUV, 193-nanometer) optical lithography. IBM claims that this technique may allow chipmakers to use current methods for seven years while continuing to achieve results predicted by Moore's Law. New methods that can achieve smaller circuits are predicted to be substantially more expensive.
Since the rapid exponential improvement could (in theory) put 100 GHz personal computers in every home and 20 GHz devices in every pocket, some commentators have speculated that sooner or later computers will meet or exceed any conceivable need for computation. This is only true for some problems—there are others where exponential increases in processing power are matched or exceeded by exponential increases in complexity as the problem size increases. See computational complexity theory and complexity classes P and NP for a (somewhat theoretical) discussion of such problems, which occur very commonly in applications such as scheduling.
Extrapolation partly based on Moore's Law has led futurists such as Vernor Vinge, Bruce Sterling, and Ray Kurzweil to speculate about a technological singularity. However, on April 13, 2005, Gordon Moore himself stated in an interview that the law may not hold for too long, since transistors may reach the limits of miniaturization at atomic levels.
| “ | In terms of size [of transistor] you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that far—but that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then they'll be able to make bigger chips and have transistor budgets in the billions. | ” |
While this time horizon for Moore's Law scaling is possible, it does not come without underlying engineering challenges. One of the major challenges in integrated circuits that use nanoscale transistors is increase in parameter variation and leakage currents. As a result of variation and leakage, the design margins available to do predictive design is becoming harder and additionally such systems dissipate considerable power even when not switching. Adaptive and statistical design along with leakage power reduction is critical to sustain scaling of CMOS. A good treatment of these topics is covered in Leakage in Nanometer CMOS Technologies. Other scaling challenges include:
- The ability to control parasitic resistance and capacitance in transistors,
- The ability to reduce resistance and capacitance in electrical interconnects,
- The ability to maintain proper transistor electrostatics that allow the gate terminal to control the ON/OFF behavior,
- Increasing effect of line edge roughness,
- Dopant fluctuations,
- System level power delivery,
- Thermal design to effectively handle the dissipation of delivered power, and
- Solve all these challenges with ever-reducing cost of manufacturing of the overall system.
Kurzweil projects that a continuation of Moore's Law until 2019 will result in transistor features just a few atoms in width. Although this means that the strategy of ever finer photolithography will have run its course, he speculates that this does not mean the end of Moore's Law:
| “ | Moore's Law of Integrated Circuits was not the first, but the fifth paradigm to provide accelerating price-performance. Computing devices have been consistently multiplying in power (per unit of time) from the mechanical calculating devices used in the 1890 U.S. Census, to [Newman's] relay-based "Robinson" machine that cracked the [German Lorenz cipher], to the CBS vacuum tube computer that predicted the election of Eisenhower, to the transistor-based machines used in the first space launches, to the integrated-circuit-based personal computer. |
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Thus, Kurzweil conjectures that it is likely that some new type of technology will replace current integrated-circuit technology, and that Moore's Law will hold true long after 2020. He believes that the exponential growth of Moore's Law will continue beyond the use of integrated circuits into technologies that will lead to the technological singularity. The Law of Accelerating Returns described by Ray Kurzweil has in many ways altered the public's perception of Moore's Law. It is a common (but mistaken) belief that Moore's Law makes predictions regarding all forms of technology, when it actually only concerns semiconductor circuits. Many futurists still use the term "Moore's Law" to describe ideas like those put forth by Kurzweil.
Krauss and Starkman announced an ultimate limit of around 600 years in their paper "Universal Limits of Computation", based on rigorous estimation of total information-processing capacity of any system in the Universe.
Then again, the law has often met obstacles that appeared insurmountable, before soon surmounting them. In that sense, Mr. Moore says he now sees his law as more beautiful than he had realised. "Moore's Law is a violation of Murphy's Law. Everything gets better and better."
Other considerations
Not all aspects of computing technology develop in capacities and speed according to Moore's Law. Random Access Memory (RAM) speeds and hard drive seek times improve at best a few percentage points each year. Since the capacity of RAM and hard drives is increasing much faster than is their access speed, intelligent use of their capacity becomes more and more important. It now makes sense in many cases to trade space for time, such as by precomputing indexes and storing them in ways that facilitate rapid access, at the cost of using more disk and memory space: space is getting cheaper relative to time.
Another, sometimes misunderstood, point is that exponentially improved hardware does not necessarily imply exponentially improved software to go with it. The productivity of software developers most assuredly does not increase exponentially with the improvement in hardware, but by most measures has increased only slowly and fitfully over the decades. Software tends to get larger and more complicated over time, and Wirth's law even states that "Software gets slower faster than hardware gets faster".
Moreover, there is popular misconception that the clock speed of a processor determines its speed, also known as the Megahertz Myth. This actually also depends on the number of instructions per tick which can be executed (as well as the complexity of each instruction, see MIPS, RISC and CISC), and so the clock speed can only be used for comparison between two identical circuits. Of course, other factors must be taken into consideration such as the bus size and speed of the peripherals. Therefore, most popular evaluations of "computer speed" are inherently biased, without an understanding of the underlying technology. This was especially true during the Pentium era when popular manufacturers played with public perceptions of speed, focusing on advertising the clock rate of new products.
It is also important to note that transistor density in multi-core CPUs does not necessarily reflect a similar increase in practical computing power, due to the unparallelized nature of most applications.
As the cost to the consumer of computer power falls, the cost for producers to achieve Moore's Law has the opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. As the cost of semiconductor equipment is expected to continue increasing, manufacturers must sell larger and larger quantities of chips to remain profitable. (The cost to tape-out a chip at 180 nm was roughly US$300,000. The cost to tape-out a chip at 90 nm exceeds US$750,000, and the cost is expected to exceed US$1,000,000 for 65 nm.) In recent years, analysts have observed a decline in the number of "design starts" at advanced process nodes (130 nm and below.) While these observations were made in the period after the 2000 economic downturn, the decline may be evidence that traditional manufacturers in the long-term global market cannot economically sustain Moore's Law. However, Intel was reported in 2005 as stating that the downsizing of silicon chips with good economics can continue for the next decade. Intel's prediction of increasing use of materials other than silicon, was verified in mid-2006, as was its intent of using trigate transistors around 2009. Researchers from IBM and Georgia Tech created a new speed record when they ran a silicon/germanium helium supercooled transistor at 500 gigahertz (GHz). The transistor operated above 500 GHz at 4.5 K (—451°F) and simulations showed that it could likely run at 1 THz (1,000 GHz), although this was only a single transistor, and practical desktop CPUs running at this speed are extremely unlikely using contemporary silicon chip techniques
Amdahl's Law
At Sandia National Laboratories, we are currently engaged in research involving massively-parallel processing. There is considerable skepticism regarding the viability of massive parallelism; the skepticism centers around Amdahl's law, an argument put forth by Gene Amdahl in 1967 [1] that even when the fraction of serial work in a given problem is small, say s, the maximum speedup obtainable from even an infinite number of parallel processors is only 1/s. We now have timing results for a 1024-processor system that demonstrate that the assumptions underlying Amdahl's 1967 argument are inappropriate for the current approach to massive ensemble parallelism.
If N is the number of processors, s is the amount of time spent (by a serial processor) on serial parts of a program and p is the amount of time spent (by a serial processor) on parts of the program that can be done in parallel, then Amdahl's law says that speedup is given by
Speedup = (s + p ) / (s + p / N )
= 1 / (s + p / N ),
where we have set total time s + p = 1 for algebraic simplicity. For N = 1024, this is an unforgivingly steep function of s near s = 0 (see Figure 1).
The steepness of the graph near s = 0 (approximately - N2 ) implies that very few problems will experience even a 100-fold speedup. Yet for three very practical applications (s = 0.4 - 0.8 percent) used at Sandia, we have achieved the speedup factors on a 1024-processor hypercube which we believe are unprecedented [2]: 1021 for beam stress analysis using conjugate gradients, 1020 for baffled surface wave simulation using explicit finite differences, and 1016 for unstable fluid flow using flux-corrected transport. How can this be, when Amdahl's argument would predict otherwise?
The expression and graph both contain the implicit assumption that p is independent of N, which is virtually never the case. One does not take a fixed-size problem and run it on various numbers of processors except when doing academic research; in practice, the problem size scales with the number of processors. When given a more powerful processor, the problem generally expands to make use of the increased facilities. Users have control over such things as grid resolution, number of timesteps, difference operator complexity, and other parameters that are usually adjusted to allow the program to be run in some desired amount of time. Hence, it may be most realistic to assume that run time, not problem size, is constant.As a first approximation, we have found that it is the parallel or vector part of a program that scales with the problem size. Times for vector startup, program loading, serial bottlenecks and I/O that make up the s component of the run do not grow with problem size. When we double the number of degrees of freedom in a physical simulation, we double the number of processors. But this means that, as a first approximation, the amount of work that can be done in parallel varies linearly with the number of processors. For the three applications mentioned above, we found that the parallel portion scaled by factors of 1023.9969, 1023.9965, and 1023.9965. If we use s' and p' to represent serial and parallel time spent on the parallel system, then a serial processor would require time s' + p' x N to perform the task. This reasoning gives an alternative to Amdahl's law suggested by E. Barsis at Sandia: Scaled speedup = (s' + p' x N ) / (s' + p')
= s' + p' x N
= N + (1 - N ) x s' In contrast with Figure 1, this function is simply a line, and one with much more moderate slope: 1 - N. It is thus much easier to achieve efficient parallel performance than is implied by Amdahl's paradigm. The two approaches, fixed-sized and scaled-sized, are contrasted and summarized in Figure 2a and b.
Our work to date shows that it is not an insurmountable task to extract very high efficiency from a massively-parallel ensemble, for the reasons presented here. We feel that it is important for the computing research community to overcome the "mental block" against massive parallelism imposed by a misuse of Amdahl's speedup formula; speedup should be measured by scaling the problem to the number of processors, not fixing problem size. We expect to extend our success to a broader range of applications and even larger values for N.
Lee Harvey Bidangan
Janus Victor Tanalgo
Kurt Enanoria
Gemmar Paron
Aiza Ibao
Rakman Camsagay Jr.
